1. Field of the Invention
The present invention relates to an analog/digital conversion circuit capable of digital conversion of an analog voltage higher than a reference voltage.
2. Description of the Related Art
FIG. 1 is a block diagram showing the configuration of an analog/digital conversion circuit of the prior art disclosed, for example, in Japanese Patent Publication No. 60-57734 (1985). For convenience of explanation, the following description assumes that the resolution of this converter is 4 bits. Between a terminal 1 where a reference voltage V.sub.ref is applied, and a ground potential point 2, is interposed a series circuit consisting of a resistor 11.sub.1 with a resistance of 3R/2 (R is an appropriate resistance value), fourteen resistors 11.sub.2, through 11.sub.15 each with a resistance of R, and a resistor 11.sub.16 with a resistance of R/2. Divided voltages of the reference voltage V.sub.ref are obtained from nodes a through o along the series circuit of the resistors 11.sub.1 through 11.sub.16 as comparison voltages proportional to the number of resistors interposed between the reference voltage V.sub.ref and the respective nodes. The comparison voltages are supplied in parallel to an analog multiplexer 12 which selects three of the comparison voltages taken from the nodes a through o to output, in accordance with a selection code and digital code supplied from a control circuit 114 for the first and second comparisons as will be described later.
The three comparison voltages selected by the analog multiplexer 12 are respectively applied to first input terminals of comparators 13.sub.1 through 13.sub.3. An analog voltage AN.sub.in inputted via a terminal 3 is applied to the other input terminals of the comparators 13.sub.1 through 13.sub.3 in parallel. The comparators 13.sub.1 through 13.sub.3 output comparison result signals C.sub.1, C.sub.2, and C.sub.2, respectively, which are supplied in parallel to the control circuit 114. In response to an analog/digital conversion start signal ST externally applied to a control input terminal 15, the control circuit 114 supplies a digital code (selection code) to the analog multiplexer 12 to select the comparison voltages to be used for the first comparison whereby the analog voltage AN.sub.in inputted via the terminal 3 for digital conversion is sorted into one of four voltage ranges that substantially quadrisect the potential difference between the reference voltage and the ground potential.
Further, the control circuit, 114 outputs a digital code according to the comparison result signals C.sub.1 through C.sub.3 supplied in parallel from the comparators 13.sub.1 through 13.sub.3, on receipt of the comparison result: signals C.sub.1 through C.sub.3 ; in the second comparison, this digital code is supplied as a selection code to the analog multiplexer 12, and when the second comparison is completed, it is supplied as it is, or with some of its values changed, depending on the result of the second comparison, as a digital conversion result to a latch circuit 16. The latch circuit 16 temporarily holds the digital code supplied from the control circuit 114, and then outputs the code via output terminals 17.sub.1 through 17.sub.4. At the completion of the analog/digital conversion, the control circuit 114 outputs a completion signal END via a control output terminal 18.
Table 1 shows the relationship between the comparison voltages obtained from the nodes a through o of the resistors 11.sub.1 through 11.sub.16 and the digital code values 2.sup.-1, 2.sup.-2, 2.sup.-2, 2.sup.-4.
The operation of the conventional analog/digital conversion circuit will be described below witch reference to Table 1.
In resXonse to the conversion start signal ST applied to the control input terminal 15, the control circuit 114 automatically outputs to the analog multiplexer 12 for the first comparison, a 4-bit selection code, "2.sup.-1, 2.sup.2-2, 2.sup.-3, 2.sup.-4 "="1100", corresponding to the node d out of the nodes d, h, and l that substantially quadrisect the potential difference between the reference voltage and the ground potential. When the digital code "1100" is inputted, the analog multiplexer 12 selects the comparison voltages (23/32)V.sub.ref, (15/32)V.sub.ref, and (7/32)V.sub.ref respectively taken from the node d corresponding to the digital code "1100", and the other two nodes h and l (not shown in FIG. 1), and respectively supplies the selected comparison voltages to the first input terminals of the comparators 13.sub.1 through 13.sub.3. When the analog voltage AN.sub.in to be converted into digital values is inputted to the other terminals of the comparators 13.sub.1 through 13.sub.3, the comparators 13.sub.1 through 13.sub.3 perform the first comparison of the analog voltage AN.sub.in with the respective comparison voltages, and supply the respective comparison result signals C.sub.1 through C.sub.3 to the control circuit 114.
When it is assumed that the comparators 13.sub.1 through 13.sub.3 output the comparison result signals C.sub.1 through C.sub.3 of the "1" level if the analog voltage AN.sub.in is higher than the respective comparison voltages, one of the following four states is obtained for the comparison result signals C.sub.1 through C.sub.3 according to whether the analog voltage AN.sub.in is higher than the respective comparison voltages.
(1) C.sub.1 =C.sub.2 =C.sub.3 ="1" level PA1 (2) C.sub.1 ="0" level, C.sub.2 =C.sub.3 ="1" level PA1 (3) C.sub.1 =C.sub.2 ="0" level, C.sub.3 ="1" level PA1 (4) C.sub.1 =C.sub.2 =C.sub.3 ="0" level
First, we will describe the case where the result of the first comparison corresponds to the state (1). When the analog voltage AN.sub.in is higher than the comparison voltage (23/32)V.sub.ref taken at the node d, the control circuit 114 outputs to the analog multiplexer 12 for the second comparison, a 4-bit selection code "1111" corresponding to the node a out of the nodes a, b, and c that substantially quadrisect the potential difference between the reference voltage and the comparison voltage (23/32)V.sub.ref at the node d. When this digital code is inputted, the analog multiplexer 12 selects the comparison voltages (29/32)V.sub.ref, (27/32)V.sub.ref, and (25/32)V.sub.ref respectively taken from the node a corresponding to the digital code "1111", and the other two nodes b and c, and supplies the selected comparison voltages to the respective comparators 13.sub.1 through 13.sub.3.
Then, the comparators 13.sub.1 through 13.sub.3 perform the second comparison of the analog voltage AN.sub.in with the respective comparison voltages.
In the second comparison, as in the first comparison, one of the above four states is obtained for the comparison result signals C.sub.1 through C.sub.3 according to whether the analog voltage AN.sub.in is higher than the respective comparison voltages. As a result of the second comparison, if the comparison result signals C.sub.1 through C.sub.3 are all at the "1" level, the control circuit 114 determines that the analog voltage AN.sub.in is higher than the comparison voltage (29/32)V.sub.ref at the node a, and passes the digital code outputted at the start of the second comparison on to the latch circuit 16. The latch circuit 16 outputs the digital code "1111" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in .
On the other hand, if C.sub.1 32 "0" level and C.sub.2 =C.sub.3 ="1" level as a result of the second comparison, the control circuit 114 determines that tile analog voltage AN.sub.in is lower than the comparison voltage (29/32)V.sub.ref at the node a, but higher than the comparison voltage (27/32)V.sub.ref at the node b, and changes the two digits of a low order, bit 2.sup.-3 and bit 2.sup.-4, of the digital code outputted at the start of the second comparison, to "10"; the thus changed digital code is supplied to the latch circuit 16. The latch circuit 16 outputs the digital code "1110" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in .
Further, if C.sub.1 =C.sub.2 ="0" level and C.sub.3 ="1" level as a result of the second comparison, the control circuit 114 determines that the analog voltage AN.sub.in is lower than the comparison voltage (27/32)V.sub.ref at the node b, but higher than the comparison voltage (25/32)V.sub.ref at the node c, and changes the two digits of a low order, bit 2.sup.-3 and bit 2.sup.-4, of the digital code outputted at the start of the second comparison, to "01"; the thus changed digital code is supplied to the latch circuit 16. The latch circuit 16 outputs the digital code "1101" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in .
If C.sub.1 =C.sub.2 =C.sub.3 ="0" level as a result of the second comparison, the control circuit 114 determines that, the analog voltage AN.sub.in is lower than the comparison voltage (25/32)V.sub.ref at the node c, but higher than the comparison voltage (23/32)V.sub.ref at the node d, and changes the two digits of a low order, bit, 2.sup.-3 and bit 2.sup.-4, of the digital code outputted at the start of the second comparison, to "00" ; the thus changed digital code is supplied to the latch circuit 16. The latch circuit, 16 outputs the digital code "1100" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in .
Next, we will describe the case where the result of the first comparison corresponds to the state (2). When C.sub.1 ="0" level and C.sub.2 ="1" level, that is, when the analog voltage AN.sub.in is lower than the comparison voltage (23/32)V.sub.ref at the node d, but higher than the comparison voltage (15/32)V.sub.ref at the node h, the control circuit 114 outputs to the analog multiplexer 12 for the second comparison, a 4-bit selection code "1011" corresponding to the node e out of the nodes e, f, and g that substantially quadrisect the potential difference between the comparison voltage (23/32)V.sub.ref at the node d and the comparison voltage (15/32)V.sub.ref at the node h. When this digital code is inputted, the analog multiplexer 12 selects the comparison voltages (21/32)V.sub.ref, (19/32)V.sub.ref, and (17/32)V.sub.ref respectively taken from the node e corresponding to the digital code "1011", and the other two nodes f and g, and supplies the selected comparison voltages to the respective comparators 13.sub.1 through 13.sub.3.
Then, the comparators 13.sub.1 through 13.sub.3 perform the second comparison of the analog voltage AN.sub.in with the respective comparison voltages.
As a result of the second comparison, if the comparison result signals C.sub.1 through C.sub.3 are all at the "1" level, the control circuit 114 determines that the analog voltage AN.sub.in is higher than the comparison voltage (21/32)V.sub.ref at the node e, and passes the digital code outputted at the start of the second comparison on to the latch circuit 16. The latch circuit 16 outputs the digital code "1011" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in .
On the other hand, if C.sub.1 ="0" level and C.sub.2 =C.sub.3 ="1" level as a result of the second comparison, the control circuit 114 determines that the analog voltage AN.sub.in is lower than the comparison voltage (21/32)V.sub.ref at the node e, but higher than the comparison voltage (19/32)V.sub.ref at the node f, and changes the two digits of a low order, bit 2.sup.-3 and bit 2.sup.-4, of the digital code outputted at the start of the second comparison, to "10"; the thus changed digital code is supplied to the latch circuit 16. The latch circuit 16 outputs the digital code "1010" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in.
Further, if C.sub.1 =C.sub.2 ="0" level and C.sub.3 ="1" level as a result of the second comparison, the control circuit 114 determines that the analog voltage AN.sub.in is lower than the comparison voltage (19/32)V.sub.ref at the node f, but higher than the comparison voltage (17/32)V.sub.ref at the node g, and changes the two digits of a low order, bit 2.sup.-3 and bit 2.sup.-4, of the digital code outputted at the start of the second comparison, to "01"; the thus changed digital code is supplied to the latch circuit 16. The latch circuit 16 outputs the digital code "1001" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in.
If C.sub.1 =C.sub.2 =C.sub.3 ="0" level as a result of the second comparison, the control circuit 114 determines that the analog voltage AN.sub.in is lower than the comparison voltage (17/32)V.sub.ref at the node g, but higher than the comparison voltage (15/32)V.sub.ref at the node h, and changes the two digits of a low order, bit 2.sup.-3 and bit 2.sup.-4 , of the digital code outputted at the start of the second comparison, to "00"; the thus changed digital code is supplied to the latch circuit 16. The latch circuit 16 outputs the digital code "1000" via the terminals 17.sub.1 through 17.sub.4 as the conversion result of the analog voltage AN.sub.in.
In cases where the result of the first comparison corresponds to the state (3) or (4), the processing performed is fundamentally the same as described above. That is, the control circuit 114 supplies a digital code "0111" or "0011" to the analog multiplexer 12, which selects the comparison voltages taken from the nodes i, j, and k or the nodes m, n, and o and supplies the selected voltages to the respective comparators 13.sub.1 through 13.sub.3. The control circuit 114 selects a 4-bit digital code from Table 1 according to the states of the comparison result signals C.sub.1 through C.sub.3, and outputs the selected digital code through the latch circuit 16.
When the second comparison is completed and the latch circuit 16 finished outputting the 4-bit digital code via the terminals 17.sub.1 through 17.sub.4, the control circuit 114 outputs a conversion complete signal END via the control signal output terminal 18.
In the above-described analog/digital conversion circuit of the prior art, the analog input voltage is converted into an n-bit digital word using the comparison voltages taken at the nodes that divide the potential difference between the ground potential and the reference potential into 2.sup.n ranges (n is a natural number). This leads to the problem that an analog voltage higher than the reference voltage cannot be accurately converted into digital values.